The invention relates to resistance-switching memory cells adapted for use at low voltage.
Integrated circuit memories are typically large arrays of memory cells connected between bit lines and word lines. In order to achieve reliable programming and reading of the memory cells within the array, memory cells selected to be programmed or read must be isolated from memory cells that are not selected. Also, as it becomes increasingly important to minimize power used by integrated circuit devices, it is desirable to minimize power consumption in integrated circuit memories. Lowering the voltage for reading and writing usually reduces power consumption. Also lowering the voltage usually allows elements of the integrated circuit device to shrink, thus reducing manufacturing cost. Therefore it is desirable to program and operate memories at lower voltages.
FIG. 1 shows a representative portion of an integrated circuit memory array in which voltages have been applied in order to program one of the memory cells. Each of the memory cells comprises a diode in series with an antifuse connected between one of the word lines and one of the bit lines in the memory array. In FIG. 1, the cell selected to be programmed is at the intersection of word line WL4 and bit line BL2. In order to program this cell, a high voltage of 9 volts is applied to word line WL4 and a ground voltage of 0 volts is applied to bit line BL2, thus applying 9 volts to selected cell 4,2 at this intersection.
To avoid programming any of the other unselected cells, other bit lines receive a voltage of 8.5 volts and other word lines receive 0.5 volts. This causes all unselected cells, for example cell 1,1 to receive a reverse bias voltage (in the reverse direction of normal current flow through the diode) of −8.0 volts. Half-selected cells (in which either the word line or the bit line receives a selected voltage) receive a forward bias voltage of 0.5 volts, which is less than the threshold voltage of the diodes, so only a small amount of current flows through the half-selected cells.
In order to avoid reverse bias breakdown, the diodes must be manufactured so that they can tolerate the reverse bias of 8 volts, and the antifuses must be manufactured to be somewhat leaky so that most of the voltage drop is across the diode and not the antifuse to assure that this relatively high voltage does not cause programming of the antifuse in unselected cells. However, during programming, the reverse leakage through the unselected cells causes power drain. In a large array having many unselected memory cells, this power drain can be considerable.
For example, in a two-dimensional array of 1000×1000 memory cells, there are one million memory cells. If only one row and one bit line are selected, there are 999×999 unselected cells all receiving an 8-volt bias, producing considerable power drain through the array. It is desirable to minimize power drain, and particularly important to minimize power drain in battery operated applications. It is also desirable to shrink the area occupied by the memory array, thereby reducing cost.
Other materials besides silicon and silicon dioxide have been considered for making some integrated circuit structures. FIG. 2a, taken from McPherson et al., “Proposed Universal Relationship Between Dielectric Breakdown and Dielectric Constant,” IEDM December 2002 paper number 26.6, shows measured values of dielectric constant and breakdown strength for about 10 materials and shows that the correlation coefficient between dielectric constant and breakdown strength is about 0.81, which indicates a high correlation between the two parameters.
McPherson et al., “Trends in the Ultimate Breakdown Strength of High Dielectric-Constant Materials,” published in IEEE Transactions on Electron Devices, Vol. 50, No. 8, August 2003, indicates that the ultimate breakdown strength Ebd of a dielectric material is found to decrease as the dielectric constant K increases. The paper indicates that great interest exists in the breakdown strength of high-K dielectrics because for CMOS technology scaling to continue, the conventional SiO2 gate-dielectric (which has a high Ebd) must be replaced. The paper gives new time-dependent dielectric breakdown (TDDB) data over a wide range of dielectric materials. The paper also discusses acceleration factor (the relationship between voltage and time to breakdown) and gives acceleration factor data for selected materials. But the McPherson et al. paper says nothing about materials used for making antifuses or diodes such as are used for making memory cells.
FIG. 2b, taken from the August 2003 McPherson paper, also examines breakdown strengths of four materials: silicon dioxide (SiO2), hafnium silicon oxynitride (HfSiON), tantalum oxide (Ta2O5), and PZT (a lead zirconate titanate ceramic), as a function of dielectric constant. (FIGS. 2a and 2b have a different appearance, but that is mainly because FIG. 2a uses log-log scales and FIG. 2b uses linear scales.)